The present invention relates to solid-state imaging apparatus in which shading of pixel signals outputted from the pixels arranged in a two-dimensional matrix can be reduced.
One as shown in FIG. 1, for example, is known as a solid-state imaging apparatus having pixels containing an amplification means for amplifying signals of photoelectric conversion device.
Referring to FIG. 1, numeral 100 denotes pixels where an example of pixel array of 3 columns by 3 rows is shown. A pixel region 150 is formed of this pixel array. Each pixel 100 consists of one photodiode serving as photoelectric conversion device and three MOS transistors. A photodiode 1 is connected to the source of a reset MOS transistor 2 having its gate connected in common along each row and is connected to the gate of an amplifying MOS transistor 3. The gates of the reset MOS transistors 2 connected in common by each row are connected to a vertical scanning circuit 30.
The drains of both reset MOS transistor 2 and amplifying MOS transistor 3 are connected to a power supply line 5 which is provided for each column. The power supply line 5 provided for each column is connected to a power supply terminal 7 through a common power supply line 6. The source of the amplifying MOS transistor 3 is connected to the drain of a row select MOS transistor 4 of which gate is connected in common by each row. The commonly connected gates of the row select MOS transistors 4 are connected to the vertical scanning circuit 30. The source of the row select MOS transistor 4 is connected in common along each column to a vertical signal line 10 so that the pixels 100 in each column are linked to each other by the vertical signal line 10.
Each vertical signal line 10 is connected to a load current source 11 which forms a source follower circuit together with the amplifying MOS transistor 3 within pixel. A signal voltage generated at the photodiode 1 of each pixel is to be read out after current amplification at the source follower circuit. The output signals of the source follower circuit are outputted to an external section by an output terminal OUT through the vertical signal lines 10, horizontal select MOS transistors 12, a horizontal signal output line 13, and an output amplifier 14. The gates of the horizontal select MOS transistors 12 are connected to a horizontal scanning circuit 20. Here a horizontal read circuit 200 is constructed by the horizontal select MOS transistors 12, horizontal signal output line 13, output amplifier 14, and horizontal scanning circuit 20.
In thus constructed solid-state imaging apparatus, photodiode 1 is reset-row by row to the level of the power supply and is caused to accumulate charge corresponding to an incident light amount by controlling row by row the reset MOS transistor 2 and row select MOS transistor 4 based on a signal from the vertical scanning circuit 30. A signal voltage due to such accumulated charge occurs row by row on each vertical signal line 10 as amplified by the source follower circuit and is outputted from the output amplifier 14 by sequentially controlling ON/OFF of the horizontal select MOS transistor 12 by means of the horizontal scanning circuit 20.
Further, FIG. 2 is a circuit diagram of solid-state imaging apparatus as disclosed in Japanese Patent Application Laid-Open Hei-11-103418. In this solid-state imaging apparatus, horizontal read circuits are provided on upper and lower sides of the pixel region and each horizontal circuit is connected to vertical signal lines of every other column. Here, like components as those in the solid-state imaging apparatus shown in FIG. 1 are denoted by like reference numerals. Referring to FIG. 2, numeral 100 denotes pixels where an example of pixel array of 4 columns by 3 rows is shown. A pixel region 150 is thereby formed. Each pixel 100 consists of one photodiode serving as photoelectric conversion device and three MOS transistors.
A photodiode 1 is connected to the source of a reset MOS transistor 2 having its gate connected in common along each row and is connected to the gate of an amplifying MOS transistor 3. The gate of the reset MOS transistor 2 connected in common by each row is connected to a vertical scanning circuit 30. The drains of both reset MOS transistor 2 and amplifying MOS transistor 3 are connected to a power supply line 5 which is provided for each column. The power supply line 5 provided for each column is connected to a power supply terminal 7 through a common power supply line 6.
The source of the amplifying MOS transistor 3 is connected to the drain of a row select MOS transistor 4 of which gate is connected in common by each row. The commonly connected gates of the row select MOS transistors 4 are connected to the vertical scanning circuit 30. The sources of the row select MOS transistors 4 are connected in common along each column to a vertical signal line 10 so that the pixels 100 in each column are linked to each other by the vertical signal line 10. Each vertical signal line 10 is connected to a load current source 11 which forms a source follower circuit together with the amplifying MOS transistor 3 within pixel. A signal voltage generated at the photodiode 1 of each pixel is to be read out after current amplification at the source follower circuit.
The pixel signals, which will become output signals of the source follower circuit, are read out using a first horizontal read circuit 200-1 and second horizontal read circuit 200-2 each connected to the vertical signal lines of every other column. The output signals of the source follower circuit of the pixel columns connected to the first horizontal read circuit 200-1 are outputted to an external section from an output terminal OUT1 through the vertical signal line 10, a horizontal select MOS transistor 12-1, a horizontal signal output line 13-1, and an output amplifier 14-1. The gates of the horizontal select MOS transistors 12-1 are connected to a first horizontal scanning circuit 20-1. Here, the first horizontal read circuit 200-1 is constructed by the horizontal select MOS transistors 12-1, horizontal signal output line 13-1, output amplifier 14-1, and the first horizontal scanning circuit 20-1.
Further, the output signals of the source follower circuit of the pixel columns connected to the second horizontal read circuit 200-2 are outputted to an external section from an output terminal OUT2 through the vertical signal line 10, a horizontal select MOS transistor 12-2, a horizontal signal output line 13-2, and an output amplifier 14-2. The gates of the horizontal select MOS transistors 12-2 are connected to a second horizontal scanning circuit 20-2. Here, the second horizontal read circuit 200-2 is constructed by the horizontal select MOS transistors 12-2, horizontal signal output line 13-2, output amplifier 14-2, and the second horizontal scanning circuit 20-2.
In thus constructed solid-state imaging apparatus, photodiode 1 is reset row by row to the level of the power supply and is caused to accumulate charge corresponding to an incident light amount by controlling row by row the reset MOS transistor 2 and row select MOS transistor 4 based on a signal from the vertical scanning circuit 30. A signal voltage due to such accumulated charge occurs row by row on each vertical signal line 10 as amplified by the source follower circuit and is outputted from the output amplifiers 14-1 and 14-2 by sequentially controlling ON/OFF of the horizontal select MOS transistors 12-1 and 12-2 of the first and second horizontal read circuits 200-1 and 200-2 by means of the first and second horizontal scanning circuits 20-1 and 20-2.